Recreating Voodoo Graphics and a Late-1990s Gaming PC on an FPGA

Summary

The author built zSST, a SystemVerilog recreation of the 3dfx Voodoo 1 graphics chip, and integrated it with a z486 CPU on a Xilinx KV260 to run DOS games with original 3D rendering at 100 MHz. The post details the fixed‑point pipeline, stage breakdown, and memory subsystem needed to sustain one pixel per clock.

• zSST implements most Voodoo1 features (triangles, texture filtering, mipmapping, depth, fog, blending) in SystemVerilog, running at 100 MHz on a KV260.
• The pixel pipeline is split into a four‑stage TMU front‑end and six FBI stages, using fixed‑point arithmetic derived from the original spec.
• Memory bandwidth is the bottleneck; four‑way interleaved texture RAM and parallel accesses are used to sustain one pixel per clock.
• All geometry transforms are done on the host z486 CPU, leaving the FPGA to handle rasterization and pixel operations.

FPGA designers and retro‑hardware enthusiasts will care because it shows how to recreate a classic 3D GPU with modern programmable logic, exposing practical pipeline and memory design trade‑offs.