Hall of FameUlrich Drepper2007397 min readpaperadvanced
What Every Programmer Should Know About Memory
Summary
The paper explains how modern CPU caches, memory controllers, and NUMA architectures affect program performance and what developers can do to write cache‑friendly code. It provides concrete advice and tooling to reduce cache misses, avoid false sharing, and place memory near the accessing cores.
- Cache lines are typically 64 B; accessing data with strides larger than this causes many cache misses—organize data for spatial locality.
- False sharing degrades multi‑threaded performance; keep per‑thread data on separate cache lines or pad structs.
- On NUMA systems, allocate memory on the node where the thread runs (e.g., numa_alloc_onnode) to avoid remote memory latency.
- Use profiling tools like perf, OProfile, or cachegrind to locate cache‑miss hotspots and verify cache‑friendly access patterns.
Performance‑critical software engineers should understand these memory details to write faster, more scalable code on commodity hardware.
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